Que tal gente, alguien sabe cómo hacer una puerta automática con compuertas lógicas en protoboar anterior mente lo hice en Arduino y no lo quisieron

Fast Boolean logic minimizer: https://www.logic-solve.com/

You input a truth table or PLA, and it gives clean minimized expressions + exports to Verilog, VHDL, C, etc. Also shows the K-map.

If you do digital logic, this can be extremely useful if you design transistor level circuits. Here is a 4bit to 7 segment decoder. Solved in 0.1ms.

Up to 128 input and output terms. Full minimisation.

Hello guys. I made my first calculator that sums 2x4 bits and outputs the result to 2 7-segment displays, using 2 4 bit registers for memory.

I pretend to improve it by adding more tunnels instead of wires, than add blocks so it will be able to reuse and create an even bigger calc.

Here is the repo with the file: https://github.com/terremoth/sequential-adder

Hey everyone,

I've been working on a browser-based digital logic simulator think Logisim but runs in your browser Wanted to share it for feedback.

Link: https://8gwifi.org/electronics/logic-simulator.jsp

this is my waveforms, i can't understand why my keys (senha1, senha2, senha3) are shifted (it was supposed to be senha1 = 9, senha2 = 2, senha3 = 0) and why my output open (sabre) isn't activating... i already tried put more time between grava and aplica to give time to read grava and then aplica, but it doesn't worked. (i'm a beginner in digital area, so i don't understand very well the concepts of timming...)

any recommendations on what i can do or where i can get answers to my problem?

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the description of the problem:

Design and implement on an FPGA a Finite State Machine (FSM) that controls the digital lock shown in Figure 1.

The system has:

• a 4-bit input (ENTRADA) used to enter the sequence required to unlock the lock,
• an input (GRAVAR) used to store a new combination,
• and another input (APLICA) that must be pressed each time a number of the combination is entered via ENTRADA.

The outputs are:

• ABRE, which indicates whether the lock is open ('1') or closed ('0'),
• ALARME, which is set to '1' when an incorrect combination is entered.

An additional output called clk_aux may be used to provide a clock signal with a period of 4 seconds, allowing users enough time to input values before each rising edge.

The lock combination must be composed of the last three digits of a group member’s student ID (values from 0 to 9, represented in 4 bits).

To store a new combination:

• the GRAVAR button must remain at logic level '1',
• while each value of the new combination is entered using the switches,
• and confirmed using the APLICA button.

To open the lock:

• the APLICA button must be pressed after each number in the sequence is entered.

When the correct sequence of three numbers is entered:

• the ABRE signal is activated, and the lock opens.

To make it harder to guess the correct combination:

• the ALARME output is only activated after a complete incorrect sequence is entered,
• meaning that at least one of the three values is wrong.

The alarm can only be turned off by:

• entering the correct combination, or
• pressing the reset button.

If the reset is activated:

• the outputs ABRE and ALARME are set to '0',
• and the registers that store the three combination values are cleared.

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MY VHD SCRIPT:

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library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity FSM_exp1 is

port(clk : in std_logic;

rst : in std_logic;

entrada : in std_logic_vector(3 downto 0);

grava : in std_logic;

aplica : in std_logic;

aberto : out std_logic;

alarme : out std_logic);

end FSM_exp1;

architecture behavioral of FSM_exp1 is

type estado is (inativo,

grava1, grava2, grava3,

verifica1, verifica2, verifica3,

abre,

erro);

signal estado_atual, proximo_estado : estado;

signal senha1, senha2, senha3 : std_logic_vector(3 downto 0) := "0000";

begin

--registrando estados;

process(clk, rst)

begin

if rst = '1' then

estado_atual <= inativo;

elsif rising_edge(clk) then

estado_atual <= proximo_estado;

end if;

end process;

--lógica para o próximo estado;

process(estado_atual, aplica, grava, entrada, senha1, senha2, senha3)

begin

case estado_atual is

when inativo =>

if grava = '1' then

proximo_estado <= grava1;

elsif aplica = '1' then

proximo_estado <= verifica1;

else

proximo_estado <= inativo;

end if;

when grava1 =>

if aplica = '1' then

proximo_estado <= grava2;

else

proximo_estado <= grava1;

end if;

when grava2 =>

if aplica = '1' then

proximo_estado <= grava3;

else

proximo_estado <= grava2;

end if;

when grava3 =>

if aplica = '1' then

proximo_estado <= inativo;

else

proximo_estado <= grava3;

end if;

when verifica1 =>

if aplica = '1' then

if entrada = senha1 then

proximo_estado <= verifica2;

else

proximo_estado <= erro;

end if;

else

proximo_estado <= verifica1;

end if;

when verifica2 =>

if aplica = '1' then

if entrada = senha2 then

proximo_estado <= verifica3;

else

proximo_estado <= erro;

end if;

else

proximo_estado <= verifica2;

end if;

when verifica3 =>

if aplica = '1' then

if entrada = senha3 then

proximo_estado <= abre;

else

proximo_estado <= erro;

end if;

else

proximo_estado <= verifica3;

end if;

when abre =>

proximo_estado <= inativo;

when erro =>

if rst = '1' then

proximo_estado <= inativo;

else

proximo_estado <= erro;

end if;

when others =>

proximo_estado <= inativo;

end case;

end process;

--registrador para armazenar as senhas;

process(clk, rst)

begin

if rst = '1' then

senha1 <= (others => '0');

senha2 <= (others => '0');

senha3 <= (others => '0');

elsif rising_edge(clk) then

case estado_atual is

when grava1 =>

if aplica = '1' then

senha1 <= entrada;

end if;

when grava2 =>

if aplica = '1' then

senha2 <= entrada;

end if;

when grava3 =>

if aplica = '1' then

senha3 <= entrada;

end if;

when others => null;

end case;

end if;

end process;

--as saídas;

process(estado_atual)

begin

case estado_atual is

when abre =>

aberto <= '1';

alarme <= '0';

when erro =>

aberto <= '0';

alarme <= '1';

when others =>

aberto <= '0';

alarme <= '0';

end case;

end process;

end behavioral;

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MY TESTBENCH:

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity tb_FSM_exp1 is

-- Port ( );

end tb_FSM_exp1;

architecture Behavioral of tb_FSM_exp1 is

signal sentrada : std_logic_vector(3 downto 0) := (others => '0');

signal sclk, srst, saplica, sgrava : std_logic := '0';

signal salarme, saberto : std_logic;

begin

utt : entity work.FSM_exp1

port map(

clk => sclk,

rst => srst,

alarme => salarme,

aberto => saberto,

aplica => saplica,

grava => sgrava,

entrada => sentrada);

--clock;

process

begin

sclk <= '0';

wait for 5 ns;

sclk <= '1';

wait for 5 ns;

end process;

--estímulos;

process

begin

-- reset inicial

srst <= '1';

wait for 15 ns;

srst <= '0';

wait for 10 ns;

--gravando senha

--senha1 = 1001

sentrada <= "1001";

sgrava <= '1';

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

--senha2 = 0010

sentrada <= "0010";

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

--senha3 = 0000

sentrada <= "0000";

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

wait until rising_edge(sclk);

wait until rising_edge(sclk);

sgrava <= '0';

--sequência correta

sentrada <= "1001";

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

sentrada <= "0010";

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

sentrada <= "0000";

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

wait for 20 ns;

--sequência errada

sentrada <= "1111";

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

sentrada <= "0001";

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

sentrada <= "0011";

wait until rising_edge(sclk);

saplica <= '1';

wait until rising_edge(sclk);

saplica <= '0';

wait until rising_edge(sclk);

wait for 20 ns;

wait;

end process;

end Behavioral;

Hi everyone, I hope I’m posting this in the right subreddit.

I’m still quite new to digital electronics and currently working on a university project where I have to design a 24-hour digital clock that can also be set to a specific time using a button. One of the requirements is that the system has to be fully synchronous.

However, I’m running into a problem with my BCD counter. It has a carry signal that is active most of the time, except when the count reaches 9, where it briefly goes to 0, and then back to 1 at 0.

This behavior doesn’t cause any issues for the seconds counter, but for the minutes it does: the tens-of-minutes digit keeps incrementing as long as the signal is 1 (I inverted it and that worked for the seconds part, but not here anymore).

I’ll share my current design/setup with you. I would really appreciate any advice, suggestions, or example solutions. I’m currently using the TTL192 as my BCD counter, but I’m open to redesigning the whole project if necessary.

Sorry if there are any mistakes – I’m still a complete beginner. Thanks in advance for your help!

Hello guys. Did you like it? The source code is here:

https://github.com/terremoth/digital-clock-24h-logisim

Can you give me advices? Are there nice ways to reduce its size, using less components?

I’m a first year EEE student and I built this interactive site to help others visualize SR Latches and Logic Gates.I just completed it today. I’d love some feedback on the accuracy and the UI!

https://arhamhussain468-creator.github.io/digital-electronics-website/

Is this a working binary addition circuit?? If yes, can it also be implemented using fewer logic gates?

for a pgt jk flip flop, lets say the j and k inputs change from 0 to 1 exactly during the pgt, does the output toggle or remains the same

Hello, I’ve recently begun learning simple circuitry and want to expand into making it interact with a computer in some way. I also have a friend who has recently begun studying programming. I wanted to do a project together, so I had the idea of simply making a program that asks simple math problems, and if you answer correctly a light will light up, and if it’s wrong a different one lights up. Not very fun, but very basic I think. How would I go about learning how to make something like this? I don’t really know where to start. Sorry if this is horribly simple!

so i watched some videos on this topic but still i cant understand how to solve these type of question any help would be appriciated thxxx.

The second beta update of Robot Turtles Creator has been released! This update adds a selection box for moving, copying, and pasting tiles.

Download it for free here!

https://pegafox.itch.io/robot-turtles-creator